Verifying Additive Phase Noise And Jitter Attenuation Of PLLs In High-Speed Digital Designs

Increasing data rates in high-speed digital designs and wireless communications require SerDes PLLs and clock synthesizers with low additive phase noise and high jitter attenuation. Modern designs often follow a two-stage architecture comprising a jitter-attenuator and a frequency-synthesizer stage. Phase noise analyzers are the choice instruments for these tests due to their high phase noise sensitivity. This application note presents a phase noise analyzer solution to test the additive phase noise and jitter transfer function of PLLs. Download the full paper for more information.