Unified Processor Architecture

Infineon Technologies 1.3 of its TriCore Unified Processor Core architecture includes a higher operating frequency than earlier versions and a new core a high-speed local memory bus to support increased levels of parallel compute operations, and an enhanced co-processor bus interface.

Additionally, the core features an integrated Memory Management Unit (MMU) to support advanced operating systems, such as EPOC32, Linux, and Windows CE.

In embedded system applications that require both real-time microcontroller (MCU) and Digital Signal Processor (DSP) functionality, the core provides raw processing rates of up to 250 MIPS when operating at 166 MHz.
New application specific standard products (ASSPs) based on Version 1.3 of the TriCore Unified Processor architecture, including products utilizing the integrated MMU, are expected to sample late in 2000.

The TriCore Unified Processor architecture is well suited for applications that previously required separate MCU and DSP components. It has already been implemented in processors for industrial computer control, automotive engine controls, and telecommunications. With the addition of the MMU, additional application categories and markets are now open to solutions based on the architecture.

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