This Algorithmic Framework Is Discovering Novel Chip Designs Never Invented Before

USC researchers invent a chip design method that could accelerate the design of the next generation of wireless devices, from 5G phones to autonomous vehicles, by unlocking designs that traditional chip engineering could never reach.

Every time you make a call over Bluetooth, connect to Wi-Fi, or let your car’s radar scan the road ahead, a tiny chip is doing the invisible work of sending and receiving radio signals. Designing those chips well has always required years of training and months of painstaking human labor. A PhD student at the USC Viterbi School of Engineering may have found a way to go further, uncovering chip designs that the traditional approach based on human intuition alone could not reach.

Vinay Chenna, working with Ming Hsieh Electrophysics Professor Hossein Hashemi in the Ming Hsieh Department of Electrical and Computer Engineering of Viterbi and the USC Stevens School of Computing and Artificial Intelligence, has developed an algorithmic framework for designing radio frequency integrated circuits, or RFICs. It works autonomously, produces results in days rather than months, and unlocks chip designs that traditional methods could not achieve.

“These chips are in every wireless device you own,” Hashemi says. “Your phone, your laptop, your car radar, space satellites.” For Hashemi, the excitement is not about what current methods can no longer do, but about what is now possible. “What Vinay has shown is that a computer can design these circuits better than the traditional methods, and do it in a fraction of the time.”

Chips That Look Like QR Codes
The way RFICs are designed today has not changed fundamentally in decades. An engineer starts with a set of target specifications, picks from a library of known circuit architectures, places familiar components like inductors, capacitors and transistors, simulates their behavior, adjusts, and iterates. The process can take a skilled team months. Even then, the result is constrained by what intuition has guided us to try.

Chenna’s algorithm throws that playbook out entirely.

It divides the chip layout into a three-dimensional grid of tiny pixels across multiple stacked metal layers, up to seven in the current implementation. Starting from a simple, human-readable structure like a spiral, it begins randomly flipping pixels: adding metal here, removing it there. After each change, it runs a full simulation to check whether circuit performance improved. If it did, the change stays. If not, it is undone. The algorithm runs continuously, trying thousands of combinations until it lands on the best possible design.

The approach is part of a broader scientific movement called inverse design, where instead of drawing a solution and testing it, you instruct a computer what outcome you want and let it work backwards to find a geometry that delivers it, however unconventional that geometry might turn out to be.

What comes out the other side looks, in Hashemi’s words, like a QR code. Quasi Random. Quasi Uninterpretable. Nothing like the orderly geometries of conventional chip design.

Onto the production line
As wild as they look, these designs are already a reality. A key constraint built into the algorithm is to only produce layouts that current foundries can make. Chenna’s chips have been fabricated by Tower Semiconductor in Newport Beach using standard manufacturing processes. The gap between what a computer can dream up and what a factory can actually build, it turns out, does not have to exist.

And it finds solutions that were completely unexpected.

“At this point, we do not have any explanation for why these geometries work,” Chenna says. “The design spaces are so large that it would be impossible to systematically explore them with current methods. The computer tries out possibilities that a human would typically not consider trying.”

It is a strange and exciting position for a scientist to be in today: uncovering solutions that work, without yet being able to explain why.

Hashemi is equally direct. After nearly 30 years designing RFICs the traditional way, he says he cannot explain why his student’s algorithmically generated designs go beyond what he could design himself. “I ask myself this question all the time. Can you explain why the computer’s design is better? And I say: at this time, no, I can’t.”

Those are not “AI Chips”
The distinction between Chenna’s work and mainstream AI chip design is important, and often misunderstood.

Most AI-assisted chip design relies on machine learning: training algorithms on large datasets of existing designs so they can predict better new ones. That approach has gained traction for digital chips, where training data is abundant. For RFICs, and especially for the kind of complex, multilayered designs Chenna is targeting, however, it hits a wall.

“According to our calculations, generating the training data needed would take several decades,” Chenna says. The number of possible layout configurations for a single component in one of his designs reaches the astronomical figure of 10 to the power of 324. Consider: There are roughly 10 to the power of 80 atoms in the observable universe. No dataset will ever be large enough.

Instead, Chenna uses a class of algorithms called metaheuristics, which explore enormous design spaces through guided randomness without needing prior examples. No training data. No neural networks. Just physics, iteration, and computing time. It is a fundamentally different approach, and it is one that scales to problems machine learning cannot currently touch.

It also opens up the full three-dimensional complexity of a real chip. Earlier work on algorithmic chip design, including research from Princeton that helped pioneer the concept, was limited to a single layer of metal. A modern integrated circuit can have up to two dozen layers. Chenna’s algorithms use several of them, which is a large part of why his chips are both higher-performing and significantly smaller. Chip real estate, he points out, costs anywhere from $5,000 to $200,000 per square millimeter. Size matters.

Many Papers, One Big Idea
The breadth of what Chenna has demonstrated in a single year is unusual. Over the past eight months he has published eight first-author papers, earned two spots at ISSCC 2026, known in the field as the Olympics of chip design, and received both the IEEE SSCS Predoctoral Achievement Award and the IEEE MTT-S Tom Brazil Graduate Fellowship, the top predoctoral honors in integrated circuits and microwave engineering respectively. Having won both at once, Hashemi notes, is extremely rare. Three papers stand out.

His first major result applied the method to power amplifiers, the components inside every wireless device that drive the antenna, and won the Best Paper Award at the 2025 RFIC Symposium. They are also the biggest drain on your phone battery. His designs, operating at the millimeter-wave frequencies used in automotive radar and high-speed wireless, achieved over 30 percent power efficiency on chips smaller than a grain of rice. “If you can double your power amplifier efficiency,” Chenna says, “you can increase the battery life of your phone by quite a bit.”

His two ISSCC 2026 papers push the method into new territory. One tackles a low-noise amplifier, the component that receives incoming signals and must amplify them without adding static. The chip covers the frequency bands used by 5G and targeted by 6G and reaches performance levels that conventional approaches have not achieved. What’s striking is how: the algorithm designed each stage of the amplifier in a way that looks wrong by textbook standards, yet together they achieve what conventional approaches could not.

A third paper, also at ISSCC 2026, applies the same method to signal filters used in receivers.

What This Means for Your Devices
The near-term implications are concrete. Design cycles that currently take expert teams six months to a year can now be compressed to days or two weeks. “Newer products would come faster to market, and they’ll perform better,” Hashemi says. “Technology can advance faster. The next iPhone can come sooner.”

Longer term, Chenna sees his algorithmic approach eventually combining with machine learning to create end-to-end design systems that require minimal input. A person defines what the chip needs to do. The algorithms handle everything else.

As for what happens to the engineers who currently do that work by hand, both researchers see a field in transition. Productivity will skyrocket first, Chenna says. The human challenge shifts from drawing circuits by hand to exploring a design space that, until now, no one even knew existed.

It is a view Hashemi holds personally, not without a touch of irony. “Algorithms and AI solutions will improve productivity, reduce time to market, and offer solutions that are far superior to and at this time unexplainable to human designs. There will be a time when far fewer human designers would be needed to accomplish the same tasks.” He pauses, with the wry resignation of someone who has spent 30 years mastering exactly the craft his work is now disrupting. “At least I was the one who contributed to this. It’s better that I do it than somebody else.”