System Generator Tool

A new System Generator tool for Simulink has been introduced. Digital signal processing (DSP) designers can use MATLAB and Simulink tools to develop and simulate complete DSP designs implemented in FPGAs. The new tool bridges the recognized gap between system-level DSP design and FPGA hardware implementation, which is crucial for designers of high-performance DSP systems such as 3G wireless base stations, voice over IP (VoIP) and digital video broadcasting (DVB) equipment. By using the Virtex-II architecture, DSP designers can now achieve up to 600 billion multiply and accumulate (MAC) operations per second DSP performance.

Traditionally, DSP designers have chosen between an application specific integrated circuit (ASIC) or an application specific standard product (ASSP), and a DSP processor or microprocessor. FPGAs combine both worlds by providing the performance and system integration of ASICs/ASSPs and the re-programmability and time-to-market benefits of processors.

As a plug-in to the Simulink modeling software, the system generator tool provides a bit-accurate model of FPGA circuits and automatically generates a synthesizable Hardware Description Language (HDL) code and a testbench. The HDL design can then be synthesized for implementation in the company's Virtex and Spartan-II FPGAs. To maximize predictability, density, and performance, the tool automatically maps the system design to the company's library of optimized LogiCORE algorithms. As a result, no redesign is necessary when migrating a design from the system description to the FPGA implementation, and only a single source of the design has to be maintained. This cuts development time and eliminates the risk for introducing design errors.

Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95214-3400. Tel: 408-879-6563; Fax: 408-879-4780.