Synopsys Offers New Design Planning Tool

Electronic design automation (EDA) tool manufacturer Synopsys has unveiled its Chip Architect system-on-a-chip (SOC) design-planning tool. The tool provides Design Compiler users with a top-down design flow that allows them to accurately account for physical effect earlier in the design process.

The Chip Architect Design Planner includes a hierarchical floor planning, embedded static timing analysis, timing-driven placement, and global routing. In addition it includes register-transfer-language (RTL) estimation, clock tree synthesis, power network planning, congestion analysis, and gate-level optimization capabilities.

According to Synopsys, the new tool is well suited for IC designs with more than 500,000 gates and operating speeds of better than 100 MHz. In addition, the tool is best suited for designs that are developed on silicon processes of 0.25µ and below.

Chip Architect is part of Synopsys' Physical Synthesis initiative, which unites logic synthesis, placement, and top-level routing. Specifically, Physical Synthesis combines the Chip Architect Design Planner with Synopsys' Design Compiler, Synthesis tool, Modular Compiler synthesis tool, and top-level routing software.

Chip Architect is available now to customers using libraries and flows from qualified semiconductor manufacturers. It also supports Synopsys' Odyssey standard cell and CBAII libraries. Pricing begins at $100,000 per license.