RISC Processor Core
The core has a fast, lean and low-power design with an enhanced cache controller with configurable 0-64 Kbytes of Data cache and 0-64 Kbytes of configurable Instruction cache. It is optimized for SOC designs that require very high-frequency, enhanced cache operation and branch prediction for superior system performance.
Key features of the core include the ability to execute ARM (version 4T) instructions, code compression, DSP extensions and fast context switching. A development board and simulator will be available for fast, flexible and accurate design.
The core, which is available for licensing, will be delivered as a hard (GDS-2 format), firm (netlist) or soft core (RTL). It is foundry independent and it will be fully validated in the most advanced 0.18u silicon process and other deep sub-micron technologies.
Pico Turbo, Inc., 860 Hillview Ct. Ste 160, Milpitas, CA 95035. Tel: 408-586-8801; Fax: 408-586-8802.