RISC-DSP Core
The device was designed specifically for applications performing signal processing and integer computation. With both RISC and DSP computing capability tightly integrated in the core the device can perform image processing and control functions far more efficiently than separate RISC and DSP cores integrated on the same silicon. The combined RISC-DSP LX5180 provides a footprint of 1.8 mm squared.
The device incorporates the Radiax DSP instruction extension to the baseline MIPS I instructions (except for un-aligned loads and stores, which are emulated in software). It also has a dual Multiply-Accumulate (MAC) arrangement to achieve a maximum of 360 million MACs per second at 180 MHz. The Radiax instructions, combined with the high performance MACs support all DSP constructs such as fractional arithmetic, rounding, saturation, and overflow protection, making application software easy to port.
The device features a low power CPU engine. The device takes advantage of its synthesizable nature by optimizing the CPU database for each specific process technology, as well as the target operating frequency. For large structured areas such as register file, the device minimizes the power consumption with custom designed techniques not available from synthesis tools. The register file uses clock gating to shut-off power when not used.
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