Motorola Introduces microRISC Technology
Motorola (Austin, Texas) has developed the M·CORE microRISC architecture which is suited for low-power applications, such as cellular phones and pagers, where battery life and system cost are critical. According to the company, this architecture is the culmination of a three-year design and development effort from the company's Semiconductor Product Sector. It is designed to be a building block for next-generation systems.
Motorola says the fundamental design goal for M·CORE is power efficiency. To accomplish this, the core's architects designed the execution and control circuitry to minimize internal signal transitions. As a result, the current architecture design runs from +1.8 VDC supplies.
"Our near-term goal is to provide a processing system which operates on a pair of AA cells," says Jim Thomas, vice president and director of Motorola's M·CORE Technology Center.
The M·CORE architecture is a load-store reduced instruction set computer (RISC) engine which executes 16-b instructions and has a 32-b internal data path for instructions and coding. The core contains a 16-entry, 32-b general purpose register file and processes instructions using a four-stage execution pipeline.
All memory operands are accessed through load and store instructions. As a result, all computational activity takes place within the internal registers. As external bus allows the core to access 8-, 16- and 32-b memories.
According to Motorola, interrupt performance and flexibility are critical design issues for today's embedded controller systems. To answer these issues, the architecture supports vector and auto-vector interrupts. The core contains dedicated logic to enable quick task switching and better interrupt support. Critical interrupts are handled through a set of separate exception shadow registers and an alternate register file.
Current silicon implementations of the core have been built with a 0.36 mm process. Using this process, the device operates at 50 MHz and occupies an area of 2.2 mm2.
A set of third-party development tools are currently available for the M·CORE architecture. These include Diab data's C/C++ compiler suites with floating point libraries, Software Development Systems' debug/simulation development environment, Integrated Systems' pSOSystem real-time operating system (RTOS), Microtec's VRTXmc RTOS, Summit Design's Virtual-CPU hardware/software co-development and verification tool, Hewlett-Packard's processor probe for emulation support, and Microware System Corp.'s software development tools. Wind River Systems and Motorola have also agreed to port Wind River's Tornado development environment and WindView system visualization tool to the M·CORE microprocessor architecture.