Memory Subsystem Generator

Databahn is a new online tool for memory subsystem generation. It generates synthesizable memory controller cores for the latest memory architectures, and automatically produces C- level verification support for the memory controller and associated memory components.

Databahn speeds SoC designs by automatically generating memory controller cores and the associated memory subsystem models for leading edge DRAM technologies. For the first time, designers can go online to select a set of memory components, specify a memory controller configuration, and then instantly receive synthesizable RTL code for the controller and C-level simulation models for the resulting memory subsystem.

This product can automatically generate C models for high-level architectural analysis and verification. The same models are used for functional verification, where they are integrated to all the leading EDA tools including: VHDL and Verilog simulators, testbench generators, hardware-software co-verification, and system-level design tools.

Users of Databahn are able to create different memory subsystem configurations, and instantly evaluate trade-offs. Options like buffer sizes, arbitration schemes, or caching strategies, can be modified to meet the needs of each specific customer application.

Denali Software, 644 Emerson Street, Suite 7, Palo Alto, CA., 94301. Phone: 650-325-7241; FAX: 650-325-5724.