ICSPAT/DSP World '99—3DSP Launches Development Tools for DSP Core

At this week's ICSPAT/DSP World showcase, Irvine, CA-based 3DSP Corporation launched a suite of development tools for its SP-5 digital signal processor (DSP) core. Using these tools, 3DSP says engineers can speed the development of design implementing the fixed-point SP-5 core.

The SP-5 DSP core is targeted at system-on-a-chip (SOC) and application-specific IC (ASIC) design for wireless applications. This core sports a superscalar instruction multiple data (SuperSIMD) architecture and can perform 600 million multiply accumulate (MMAC) instructions while consuming only 300 mW power. Sporting a 2.4 mm2 footprint, the SP-5 core also delivers a memory-to-register feature and a load-and-store architecture.

3DSP's new development tools include a cycle-accurate C simulation model of the SP-5 core to assist in software debugging. The tools also house a simulator that offers hooks to support advanced break-pointing capabilities, code profiling, file input/output (I/O) management, and symbolic linkage to the assemble code and C source code. Additionally, the suite sports a C compiler that is optimized to take advantage of the SP-5 core's architecture.

3DSP's development tools sport a hardware development platform with a graphical user interface (GUI) debugger that runs in a Windows environment. Features include single-step, breakpoint insertion, and JTAG port access to the SP-5 core.

The SP-5 development tools are available now. For additional information, contact 3DSP at 949-260-0156.

Edited by Robert Keenan