How To Make Wireless Communication Faster Without Wasting Power

Qilong Liu defended his PhD thesis at the Department of Electrical Engineering on October 21.

Wireless communication systems need to process increasingly wide signals while keeping power consumption and hardware complexity under control. Analog-to-digital converters (ADCs), which translate real-world analog signals into digital data, are essential to this process. However, designing converters that combine high bandwidth, reliable operation, and low power consumption is becoming increasingly challenging. PhD researcher Qilong Liu investigated a multi-stage converter architecture that addresses these competing demands through improved design methods and simpler circuit connections. The resulting prototype achieves a signal bandwidth of 360 MHz and a dynamic range of 68 dB, with measured performance reported as state of the art among comparable broadband continuous-time multi-stage converters.

Continuous-time delta-sigma modulators (CT DSMs) are attractive for wireless communication because they reduce quantization noise and provide built-in filtering to prevent aliasing. However, increasing their bandwidth becomes difficult as maintaining stability and suppressing noise require increasingly complex designs. Qilong Liu investigated continuous-time multi-stage noise-shaping converters (CT MASH ADCs), which combine several lower-order modulators to achieve wider bandwidths efficiently. The challenge is to manage how signals and quantization errors travel between stages. New analytical tools developed in this research help designers understand these interactions and balance signal quality, noise suppression, and circuit complexity.

Keeping high-speed converters reliable
Small timing delays can affect the stability of high-speed converters. The thesis analyzes techniques for compensating for excess-loop delay and introduces new sensitivity functions to assess how variations in the compensation circuit affect robustness. These tools help designers select appropriate techniques based on clocking requirements, stability, and implementation tolerances. The research also identifies the maximum noise transfer function value (NTFmax) as an important factor in the robustness of multi-bit modulators.

Simpler connections, better efficiency
The research shows that signal handling, quantization-noise filtering, and signal-leakage suppression must be optimized together. Although connecting stages through multiple paths can offer theoretical benefits, practical issues such as calibration, analog tuning, and circuit imperfections can outweigh them. Simple one-path or two-path connections are often preferable, sometimes combined with additional filtering to reduce unwanted signals, particularly when strong out-of-band interference is present.

Validated in silicon
The proposed methods were tested in a prototype three-stage CT MASH ADC fabricated in 40-nanometer CMOS technology. It achieved a signal bandwidth of 360 MHz and a dynamic range of 68 dB. The design combines low-order loop filters, passive excess-loop-delay compensation, and efficient transconductance-capacitor (Gm-C) circuits to limit power consumption and implementation complexity.

The results demonstrate that careful architectural choices can deliver high-performance broadband conversion without unnecessarily complex circuitry. The design methods developed in this thesis could help engineers build efficient ADCs for future wireless communication systems that need to handle increasingly wide signal bandwidths.