FIR Filter Generator

Xilinx, Inc.E Finite Impulse Response (FIR) Filter generator was designed for use with the company's Spartan and Virtex family of FPGAs. Xilinx, Inc.E FIR Filter delivers equivalent performance at approximately 70 percent cost-savings over programmable DSPs with the flexibility and time-to-market advantages of an FPGA. They are now able to address high-volume markets such as wireless, digital communication systems, digital TV, high-speed DSL, cable modems, and medical imaging systems.

The FIR Filter is parameterizable supporting 2-to-256 tap impulse response, 1-to-32 bit input data/coefficient precision, and a wide range of high-performance filter features including: half-band, Hilbert transforms, and interpolated filters. An implementation methodology known as "distributed arithmetic" efficiently maps filters to the FPGA architecture. Using designer specifications, the tool automatically generates a FIR filter including netlist, VHDL/Verilog simulation models, and VHDL/Verilog instantiation code.

By employing Smart-IP Technology, the generator maintains performance over the entire range of FPGA densities.
Using the FIR Filter generator, a 16-bit, 16-tap FIR filter can be implemented in an XC2S15 Spartan-II device at a 70 percent cost-savings.

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