DSP IP Cores

Three digital signal processing (DSP) intellectual property (IP) cores has been developed for wireless applications. developed using a patented ManArray architecture, the new cores feature one (2010), two (2020), or four (2040) separate indirect very long instruction word (iVLIW) execution units operating and communicating with a direct memory access (DMA) controller over a configurable database.

The first core, the BOPS2010 DSP core, is deigned for GSM and CDMA handset designs. This core can be used in fixed- or floating-point applications, can handle 1 to 4 billion operations per second, and can perform 0.4 billion multiply-and-accumulates (MACs).

The second core, dubbed the BOPS2020, is a single processing unit DSP used in tandem with a DMA processor to offer a core with balanced input/output (I/O) and computational capabilities. Specifically targeted at base station and wireless local loop (WLL) applications, the new core delivers 2 to 8 billion operations per second and 0.8 billion MAC performance.

The BOPS2040 rounds out the new series of DSP cores. Geared toward base station and WLL designs, the new DSP core can be used in fixed- and floating-point designs, features a 4 to 32 billion operations per second capability, and delivers 1.6 billion MAC performance.

The clock speed of the three DSP cores is dependent on physical design, logic parameters, process geometry, and technology.

BOPS, Inc., 101 University Avenue, Suite 410, Palo Alto, CA 94301 Phone: 650-330-8400; Fax: 650-330-1086