DAC 99—CynApps Creates HDL Environment in C/C++

Electronic design automation (EDA) startup CynApps (Santa Clara, CA) has announced new design methodologies and product support to raise the level of abstraction available to the hardware designer by creating a hardware description language (HDL) environment in C and C++. Unveiled at the Design Automation Conference (DAC), the CynApps approach is centered around Cynlib, a C++ class library for hardware description, simulation, and synthesis.

Cynlib provides the foundation for hardware design using the C language. The Cynlib classes allow the hardware designer to express design intent in a way that can be both simulated accurately and synthesized using the resistor-transistor-level (RTL)-based design methodology. Both the target logic and the system environment can be written in C++ using the Cynlib classes, making it especially well suited to system-on-chip (SOC) designs.

Cynlib contains a fully functional cycle-based simulator, which provides cycle-accurate functionality and while shielding C/C++ developers from creating their own simulation code. Cynlib also offers a clean interface to standard Verilog simulators using modular PLI interface.

Upcoming CynApps products will enable hardware architects and designers to use their familiar C environment for the initial design activities, bridging the gap to standard RTL synthesis and back-end tools. This approach will incorporate proven design practices and existing computer-aided design (CAD) flows with object-oriented capabilities provided through standard C++ compilers.

For more information on Cynlib or CynApps, call 408-588-4000.