By Ian Beavers and Matt Felmlee
As high speed signal acquisition applications using multiple analog-to-digital converters (ADCs) increase in complexity, each converter’s complementary clock solution will dictate the dynamic range and capacity of the system’s potential. With the increase in sample rate and input bandwidth of emerging giga sample per second (GSPS) ADCs, the capability and performance of the system’s distributed sample clock becomes critical. System solutions that target high frequency measurements, such as electrical measurement instrumentation and multi-converter array applications, will need leading edge clocking solutions. To read the full paper, download the available application note.