Chameleon Introduces Reconfigurable Communications Processor Family

Sunnyvale, CA-based Chameleon Systems Inc. is offering a high-bandwidth reconfigurable communications processor (RCP). Powered by the company's proprietary eConfigurable technology, the CS2000 family of communications processors provides a complete and verified reconfigurable platform that delivers 24,000 16-bit MOPS (million operations per second), 3,000 16-bit MMACS (million multiply-accumulates per second), and 50 channels of cdma2000 chip-rate processing.

The initial market for the CS2000 family is communication infrastructure. Applications include second- and third-generation wireless basestations, fixed-point wireless local loop (WLL), smart antennas, voice-over-IP (VoIP), secure communications, very high-bit-rate digital subscriber line (DSL), and communications applications that have traditionally used reprogrammable devices such as DSPs and FPGAs.

Each product in the CS2000 family has a 32-bit RISC Processor (licensed from ARC Cores, UK), a full-featured memory controller, a PCI controller, and a reconfigurable processing fabric, all of which are interconnected through a system bus. The company optimized the CS2000 architecture for implementing the full range of algorithms used in processing-intensive applications. Storage, datapath, and control functions are precisely partitioned in the architecture to afford maximum performance and flexibility.

The reconfigurable processing fabric within the CS2000 family comprises an array of reconfigurable tiles used to implement the desired algorithms. Each tile contains seven 32-bit reconfigurable datapath units (DPUs), four blocks of local store memory (32 bits wide by 128 words deep), two 16x24-bit multipliers, and a control logic unit. The tiles are organized in slices, with three tiles per slice. Initially, Chameleon will offer products containing 12, six, and three tiles.

The PCI controller itself is fully tested for PCI 2.2 compliance. The CS2000's memory controller offers a seamless memory interface to commonly desired storage devices. The controller provides a 64-bit wide port that operates at a full 125Mhz data rate, and supports SSRAM, SDRAM, and Flash EEPROM with up to a 1GByte-per-second transfer rate.

Pricing and availability
The first product in the CS2000 family, the twelve-tile CS2112, will sample in Q3 2000. Pricing will begin at $295 each in 100 piece quantities. In 2H 2001, high-volume pricing is expected to decrease to the equivalent of less than $1.00 per cdma2000 chip-rate processing channel. The C~SIDE development tools will ship in Q3 of 2000 as well, priced at $25,000 for the complete software suite.

Edited by Kristin Keiser