Cadence, Denali Partner To Speed Verification of SOC Designs

San Jose, CA-based Cadence Design Systems and Palo Alto, CA-based Denali Software have announced an agreement to integrate Denali's Memory Modeler with the Cadence Affirma family of hardware description language (HDL) simulators. This integration allows end users to generate customized memory models and to increase the simulation performance of system-on-a-chip (SOC) designs.

Under the agreement, Denali's Memory Modeler tool will be integrated with the Cadence Afforma SimVision environment, which is the graphical user interface to the Cadence logic simulators. According to both companies, this will provide customers with a smooth integration flow and a uniform look and feel across Cadence simulator products.

The Memory Modeler uses Denali's specification of memory architecture (SOMA) language to simplify the design of memory architectures and enable distribution of memory component and cores across the Internet. Modeler creates memory components for SOC applications and can be tailored to key memory specifications including static random-access memory (SRAM), flash, EPROM, and dynamic random-access memory (DRAM).

Memory Modeler is available immediately from Denali for $5,000. For more information, contact Denali at 650-325-7241.