Aptix Launches Module Verification Platform; Receives Motorola Contract

San Jose, CA-based N/A has unveiled its module verification platform (MVP), which provides engineers with the ability to drive test benches through individual prototyped design blocks or entire prototyped systems.

MVP consists of several software modules and specific hardware modules used to drive vectors of virtually unlimited depth at hundreds of kHz to MHz speeds. Vector widths up to 400 signals wide are supported. Co-simulation through the PLI interface standard is also supported for Synopsys' VCS, Cadence's Verilog XL and Model Technology's ModelSim simulators.

The MVP can run in either the vector debug or mixed signal co-simulation mode. In the vector debug mode, the MVP drives vectors and compares the output with the expected results, independent of a simulator. Automatic generation of system clocking is allowed, and bi-directional signals are supported. In co-simulation mode, users can model their designs in the Aptix system while their test bench is running from their simulator.

MVP is available for Aptix' System Explorer MP4 and the System Explorer MP3C products.

Motorola contract
On a related note, Aptix has signed a contract with Motorola, the Schaumburg, IL-based wireless system and equipment developer. Under the agreement, Motorola will use Aptix's System Explorer MP3C systems at various US locations to emulate its next-generation digital wireless designs. In addition, Motorola has purchased upgrades for its existing system Explorer MP3 products.

Aptix's System Explorer is a reprogrammable system for integration of software with custom logic, off-the-shelf components, and hard or soft intellectual property (IP). Hardware debugging is performed with off-the-shelf logic analyzers. Software debugging is accomplished debugged using in-circuit emulation capabilities. Typical circuits prototyped on the System Explorer product family operate at frequencies from 10 to 30 MHz, enabling real-time verification of many embedded applications.

The block-based verification methodology of the System Explorer product family provides a mechanism to map and verify individual design blocks incrementally and in parallel with the design creation process. According to Aptix, this approach shortens the "net" prototype creation time to achieve real-world operation of the prototype to the few days required to map and verify the last RTL block designed.

For additional information on MVP or System Explorer, contact Aptix at 408-428-6200.

Edited by Robert Keenan