APLAC RF Design Tool Reaches Version 8.00

Espoo, Finland -- N/A has launched a new release of its APLAC RF Design Tool. APLAC version 8.00 automates expert procedures to combine RFIC and analog simulation with a broad range of functions for circuit analysis and optimization.

The APLAC development team focused on simulation speed when creating the new release. As a result, APLAC RF Design Tool version 8.00 runs transient analysis simulations up to 40 times faster than the previous release, with the same accuracy. In addition, its threaded harmonic balance (HB) analysis speeds simulation significantly on multiprocessor systems.

"As usual, the new APLAC release includes several fresh, up-to-date features and models for RFIC and system-level design," APLAC CTO Olli Pekonen said. "New and enhanced technologies include an enhanced WLAN Library that supports IEEE 802.11a and 802.11b standards, IBIS modeling capability, and considerably enhanced transient and HB analyses."

"APLAC has also broadened its programming capabilities by introducing a handy C-language interface. This enables users to load their own device model codes or function codes into the APLAC Simulator, dynamically," Markus Heikkinen, product manager, noted.

APLAC RF Design Tool version 8.00 is available for Windows, Linux, and Unix platforms. Licensing options range from stand-alone portable licenses to floating network schemes. For availability or detailed information, contact APLAC.

For more information, please download What's New In APLAC 8.00.

Source: APLAC Solutions