AccelChip Offers Linear Algebra Cores Through Xilinx's Alliance Program
AccelChip's matrix inverse and factorization cores are being offered through Xilinx's third-party Alliance Program. The Alliance Program, which includes independent core developers, is designed to produce a broad selection of industry-standard solutions dedicated for use in Xilinx programmable logic.
The AccelChip cores directly implement linear algebra-based matrix operations used in applications such as sensor array processing, beamforming, global positioning, radar/sonar, Kalman filtering, and wireless communication applications. Targeted at hardware designers and system engineers who implement these applications in silicon, AccelCore DSP IP delivers synthesizable, VHDL/Verilog linear algebra cores that are highly optimized in terms of speed, power, and size.
"Our DSP customers use a combination of both HDL and Xilinx System Generator for DSP Design," said David Squires, Director of DSP Marketing in the DSP Division at Xilinx. "The addition of AccelCore into the Xilinx Alliance Program has the potential to save months of development time, regardless of design entry methodology with proven linear algebra-based matrix cores for advanced wireless and signal processing applications."
"IP is fast becoming an essential element of DSP design, thanks to its ingrained reusability and ever-increasing quality," said Dr. Tom Cesear, chief scientist at AccelChip Inc. "The Xilinx Alliance Program evaluates cores for listing in the program by certifying that they have been fully synthesized, placed and routed on Xilinx FPGAs. AccelChip is proud to work with Xilinx to now offer AccelCore DSP IP in the FPGA industry's largest 3rd-party IP program."
The initial offering of AccelCore DSP IP available through the Xilinx Alliance Program includes QR matrix factorization and inverse, Cholesky matrix factorization and inversion, and singular value decomposition (SVD).
Simulation models for AccelCore DSP IP are available from AccelChip to test and simulate their functionality and throughput in customer designs. Each AccelCore is available separately under the standardized Xilinx SignOnce IP License agreement.
SOURCE: AccelChip Inc.