Synopsys, Hitachi Provide Models For Microprocessor Cores

Mountain View CA-based Synopsys has teamed with San Jose, CA-based Hitachi, Ltd. Under the agreement, the two companies will jointly develop and distribute the first co-verification models of Hitachi's SH3-DSP and SH-4 microprocessor cores.

This agreement will make it possible for designers using the SH3-DSP and SH-4 core series to take advantage of Synopsys' Eaglei hardware/software co-verification tools during the development process. The Eaglei tools allow designers to extend their current hardware design and software development methodologies to support the concurrent verification of the two parts of the design, long before prototype availability. Instead of discovering errors in their hardware/software interfaces or misinterpretations in the system specification at the prototype phase, find them when they first appear, even at the earliest post-partitioning stage of your design.

The Eaglei tools do not require a physical prototype for hardware/software integration and verification. By not requiring this prototype, the integration point can be moved to much earlier in the design process.

The Eaglei hardware/software co-verification tools are part of a powerful suite of Synopsys high-level verification products and services, which also includes the VCS Verilog simulator, the Cyclone/VSS VHDL simulator, a range of proven logic modeling intellectual property (IP) models for simulation, and the VERA testbench automation and analysis products.

Synopsys and Hitachi will develop models for the SH3 and SH-4 cores using Eaglei's ModelLink development tool kit. The first models will be available in third quarter of 1999.