Cambridge, UK-based ARM introduced the PrimeCell Peripherals and AMBA 2.0 on-chip bus specification, in a move aimed at accelerating system-on-chip (SOC) development and advancing design reuse.
The PrimeCell Peripherals are AMBA bus-compliant, intellectual property (IP) cores developed by ARM for SOC integration. With ARM's PrimeCell Peripherals, designers can concentrate resources on SOC development, rather than dividing efforts between designing the peripherals and then developing the SOC.
The AMBA bus specification is an established, open bus standard that serves as a framework for SOC designs.
The new specification, AMBA 2.0, aligns the bus to synthesis design flows, and is targeted for performance. Since the AMBA specification is processor- and technology-independent, it enhances the reusability of peripheral and system macrocells across a wide range of IC processes.
The ARM PrimeCell Peripherals are developed using an advanced reuse methodology to provide "right-first-time" functionality for licensed IP. All peripherals are supplied in VHDL and Verilog, and are delivered with logic synthesis scripts, test benches with source code, extensive technical documentation, and product design and SOC integration manuals. Available cores include a UART, SDRAM controller, synchronous serial interface, real time clock, audio codec, general purpose I/O, smartcard interface, and color LCD controller. Additional PrimeCell Peripherals will be added in the future to meet evolving customer system requirements.
The AMBA specification consists of two bus architectures: a system bus and a peripherals bus. The system bus connects the embedded processor to high-performance peripherals, on-chip memory and interface functions, and supports multi-master bus management.
General-purpose peripherals reside on the advanced peripheral bus (APB) with connection to the system bus via a bridge, which helps reduce system power consumption and design complexity. The new specification, AMBA 2.0, adds an advanced high performance bus (AHB). The AHB's single active rising edge clock enables high bus speeds as well as logic synthesis for easy implementation. AHB offers data bus widths of 32/64/128 b, extendable to 1,024 b for high-bandwidth, data-intensive applications using wide on-chip memory.