Before the invention of transistors, computers in the 1960s were bulky, unreliable and created tremendous amounts of heat. However, with the advent of transistors and their aggressive scaling, computers today contain millions, or even billions, of transistors to complete tasks and engineers are able to pack them into small spaces such as phones, tablets, or sensors. Even with these advances, it is becoming more difficult, due to the various challenges imposed by the increasingly smaller size of devices, to keep up with Moore’s Law, which holds that the number of transistors on integrated circuits doubles approximately every two years.
CSL and Electrical and Computer Engineering faculty member Deming Chen is researching a new transistor material, graphene, which has drawn recent attention due to its outstanding electrical properties.
“Graphene is a novel emerging device,” Chen said. “We’re still trying to explore the device level characteristics and trying to understand it better.”
Graphene is a sheet of carbon atoms, which are tightly packed into a two-dimensional honeycomb lattice. It is a zero bandgap material, which makes it an excellent conductor by nature, but also leads to challenges for building transistors, which require semiconducting properties instead. To solve this, graphene is fabricated into semiconducting nano-ribbons to form the transistor channel. Chen, along with graduate student Christine Chen, and former students Artem Rogachev, Amit Sangai and Morteza Gholipour, are using this material to build transistor models because of its low-power computing capabilities and its unique physical characteristics that could potentially be used in the future in areas such as low-power electronics, medical sensors, or optical electronics.
Chen, whose research on graphene is funded by the National Science Foundation (NSF), is working to determine what, if any, benefits there are from using graphene; how graphene compares to other transistors currently used; under what conditions the material will work the best; and how close current technology is to using graphene most effectively. The team evaluated graphene under ideal circumstances and non-ideal circumstances, including the process variations, like edge roughness or oxide thickness. The non-ideal conditions show where people will need to focus their attentions to improve the fabrication techniques to reduce the negative impact of non-idealities.
Chen and his students are the first group to systematically evaluate the effect that different process variations have on graphene-based digital circuits, such as oxide thickness, effective channel length, density of doping into the graphene device, width of the graphene nano-ribbon (GNR), or GNR edge roughness. To achieve this goal, Chen and his team developed the first parameterized SPICE-compatible GNR field-effect transistor (GNRFET) models and modeled process variations, as well as enabled circuit-level simulations of GNRFET.
They evaluated two types of GNRFETs — metal-oxide semiconducting (MOS) type and Schottky-Barrier (SB) type — and compared their delay, power, energy-delay product and noise margins against complementary metal-oxide semiconductor (CMOS) technology (such as FinFET) for futuristic technology nodes ranging from 16nm down to 7nm. The evaluation showed that graphene has incredible potential under ideal circumstances, but under non-ideal circumstances, where process variations are considered, there are significant areas where improvement needs to be made.
“We wanted to tell the research community how much gap there is potentially between where we are now and where the graphene technology could be,” Chen said. “We gave the research community the precise evaluation of how far away we are from the real potential of GNRFETs, and we are the first group that can precisely measure this gap and give people quantifiable results.”
Chen and his team have been busy in 2013 and 2014 presenting various aspects of their new findings about GNRFET circuits at various occasions, including presenting their papers at the Conference of Design, Automation and Test in Europe in March 2013 and March 2014 (DATE’13 and DATE’14), the International Symposium on Nanoscale Architectures in July 2013 (NanoArch’13), the International Symposium on Low Power Electronics and Design in September 2013 (ISLPED’13), along with two workshop presentations separately organized by NSF and a group of EDA (electronic design automation) researchers. Meanwhile, the team is preparing several journal submissions based on these new findings and new GNRFET designs that mitigate the effect of process variations.
The researchers are excited about the impact their work has generated and the future uses of graphene. They have made their model available to researchers online through nanoHUB.org, with the hopes that others will build on top of it and explore other novel graphene devices. Since its release, they already received contact from other researchers inquiring about the model and sharing their experiences of using the model.
“We can see huge potential here and are excited about the future prospects of creating graphene transistors, but there is the reality of where we’re at now. If we cannot mitigate the effects of variations in the future, we won’t get to the ideal,” Chen said.
SOURCE: University of Illinois at Urbana-Champaign